(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of increasing the dense-line processing window. This increase in the dense-line processing window most preferably to be applied to the creation of memory cells using a deep-ultra violet exposure process.
(2) Description of the Prior Art
The formation of semiconductor devices requires a number of different but cooperative technologies that are aimed at creating devices that meet functional specifications at a competitive cost. The formation of integrated circuits typically takes place on the surface of a semiconductor substrate and requires the deposition and formation of such disparate circuit components as resistors, transistors, diodes, capacitors and inductors. By interconnecting the various electrical components that constitute an electrically functioning unit, the semiconductor device is completed.
Conductive interconnect lines and interconnect vias and contact points form an important part of the creation of a semiconductor device. The conductive interconnects are mostly patterned in layers of dielectric and are separated by layers of insulator materials.
The semiconductor industry has, since its inception, been characterized by a relentless and seemingly never ending drive at improving device performance while keeping device manufacturing costs under competitive control. Improvements in device performance are mostly achieved by reductions in device size and device feature size, reductions that concurrently enhance and facilitate increased device packaging. Device interconnect lines have consequently also felt the impact of this continuous reduction in device dimensions. Current technology is therefore at the point where a line width of deep sub-micron values of as low as 0.1 xcexcm is approached.
Conventional processes of creating interconnect lines and other circuit features require the exposure of patterns that are contained within for instance an optical mask, whereby these patterns are projected onto a target surface. This target surface can be a layer of photoresist, the surface of a substrate or the surface of any of the other layers of material that are used in the creation of semiconductor devices such as layers of dielectric or insulating material. With the decrease in interconnect size, the design and resolution capabilities of the exposure methods are placed under ever more stringent demands. Typical of these performance parameters of optical exposure systems are the minimum feature size that can be created using the system, the error that is incurred while performing the exposure, the uniformity of the exposure in the exposed surface, and qualities of the mask that is used that can result in errors of exposure such as the line size of the image on the mask and the size of the defect that can be allowed in the mask image while still creating high quality exposures. The indicated parameters are however not the only parameters that can be used to create ever finer interconnect line images. The source of radiation that is used for optical exposures has a given wavelength, current photolithographic exposure systems operate using near ultra violet (NUV) radiation with a wavelength of 365 nm. Using such a source of exposure allows for line width of about 0.35 um. For further decreases in line width, the wavelength of the radiation that is used to create the target image must be decreased leading to sources of exposure that operate in the deep ultra-violet (DUV) range with a wavelength of 254 nm. The DUV wavelength application allows for feature interconnect line widths down to about 0.18 um.
Semiconductor devices are typically fabricated by the creation of a multiplicity of conductive regions on the surface of a semiconductor substrate. These conductive regions are isolated from each other by dielectric layers that can contain dielectric materials such as silicon dioxide (xe2x80x9coxidexe2x80x9d) or silicon nitride (xe2x80x9cnitridexe2x80x9d), tetra-ethyl-ortho-silicate (TEOS) based oxides, boro-phosphate-silicate-glass (BPSG), phospho-silicate-glass (PSG), boro-silicate-glass (BSG), oxide-nitride-oxide (ONO), and the like. Some of the dielectrics, such as silicon dioxide, can be grown on the surface of the substrate or can be physically deposited by for instance a sputtering process or by other chemical methods of dielectric deposition. The native properties of a dielectric can further be altered by doping the dielectric layer by either n-type dopants such as arsenic and phosphorous or p-type dopants such as indium or boron. The method of forming the dielectric layer and the doping that is applied to this layer is determined by various device and processing considerations.
To create interconnect lines in the various layers of dielectric that are applied in the structure of a semiconductor device, an interconnect line pattern must be created in the dielectric. This interconnect line pattern is filled with a metal that can contain aluminum, tungsten, titanium nitride, molybdenum, silicide and polysilicon but typically contains aluminum, tungsten, wolfram or copper. Openings are created that establish electrical contact between overlying layers of interconnect lines, these openings can be further differentiated between contact openings and via openings.
The process of creating an interconnect line pattern starts with the deposition of a layer of dielectric (the dielectric into which the interconnect pattern is to be created) over which a layer of photoresist is deposited. The layer of photoresist is patterned in accordance with the desired interconnect line pattern, the photoresist is removed from above the layer of dielectric in accordance with the pattern for the to be created interconnect lines. The dielectric layer is then etched, that is the dielectric is removed in accordance with the pattern of the interconnect lines. A dry etch is typically performed, exposing the dielectric layer to a plasma that is created by using one or more gasses that expose the surface of the oxide where the photoresist has been removed. To avoid distortion of the photoresist patterns that are used to create the interconnect lines on the dielectric layer, Anti Reflective Coating (ARC) is frequently applied over the surface of the opening.
Further innovation is required in the art of creating interconnect lines if these lines are to meet future requirements of device design and creation. The literature of the art contains a large number of proposals and inventions that apply to this field. These inventions may address specific aspects of the process of forming narrow lines, such as a method that is particularly applicable to forming lines within advanced Field Effect Transistors (FET""s) whereby the line width can be as small as 0.25 um. Such a method of etching can use NUV (with a wavelength of 365 nm) photolithographic exposure and may make use of the available properties of a Anti-Reflective Coating (ARC). Other methods address the patterning of a particular layer of material by using NUV photolithographic exposure, for instance a layer of silicon nitride, to an aperture width of the etched openings of about 0.30 um, an application that holds particular promise for the formation of Field Isolation (FOX) regions in the surface of a substrate. The application of layers of ARC has in the literature on the subject also been treated extensively, such as for instance the use of silicon or silicon nitride that is interposed between a metal nitride ARC and an acidic functional photoresist layer.
The objectives of the above cited and other methods that address the formation of interconnect lines in the art can be summarized as follows:
the formation of interconnect lines that are as narrow as 0.1 urn by using Near Ultra Violet (NUV) photo exposure technology
the design and application of methods that allow for the creation of narrow lines with line size down to 0.1 um, and
the discovery and application of materials that allow for the creation of narrow lines down to a line width of 0.1 um.
U.S. Pat. No. 5,858,620 (Isihashi et al.), cited by the inventor, teaches a method for forming photoresist lines.
U.S. Pat. No. 5,955,227 (Tsujita et al.) shows a method of setting the interconnect width.
U.S. Pat No. 5,958,656 (Nakao) shows another phase shift mask (PSM) method.
U.S. Pat. No. 3,779,806 (Gipstein et al.) defines Mask Error Factor (MEF).
A principal objective of the invention is to provide a method of resolving line resolution when creating a variety of dense lines.
Another objective of the invention is to resolve problems of line resolution when creating dense lines whereby equal line spacings and adequate Depth Of Field for the exposed line pattern is assured.
Yet another objective of the invention is to provide a method of creating dense lines thereby taking advantage of a decreased Mask Error Factor of an applied Alternate Phase Shift Mask (APSM).
A still further objective of the invention is to provide a method that allows for the sizing or adaptation of layer design rules without affecting or changing device parameters.
A still further objective of the invention is to provide a method that assures that large changes in the mask chrome Critical Dimension will have a minimum impact on the image Critical Dimension thereby reducing the Mask Error Factor to close to zero.
A still further objective of the invention is to provide a method of creating dense lines that is aimed at allowing a smaller ratio of line spacing to line width (the duty ratio).
In accordance with the objectives of the invention a new method is provided for the creation of dense lines. As a first step of the invention, the mask layout is modified such that the ratio of line width (L) to line spacing (S) is sharply decreased. The line pattern that is created using this mask reflects the same sharp reduction in the ratio L/S. The width of the thus created lines is, as a second step of the invention, increased by the process of thermal flow whereby the spacing between the lines is concurrently decreased by the same amount.